Time domain symbol receiver

ABSTRACT

Methods and apparatus are described for time domain signals. An apparatus includes an electrical circuit decoder coupled to a receiver.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of, and claims a benefit of priorityunder 35 U.S.C. 120 from copending utility patent application U.S. Ser.No. 14/499,167, filed Sep. 27, 2014, which in-turn is a continuation of,and claims a benefit of priority under 35 U.S.C. 120 from utility patentapplication U.S. Ser. No. 12/074,551, filed Mar. 3, 2008, which in-turnis a utility of, and claims a benefit of priority under 35 U.S.C. 119(e)from provisional patent application U.S. Ser. No. 60/904,689, filed Mar.1, 2007, the entire contents of all of which are hereby expresslyincorporated herein by reference for all purposes.

BACKGROUND INFORMATION Field of the Invention

The field of the invention is broadly the modulation of certain carriermedia for the purpose of transmitting information between two spatiallyseparated points. More particularly, the invention addresses aparticular method and use of pulse-width modulation (PWM) for theencoding of digital data into certain physical signals prior totransmission and the decoding of such signals back into a representationof the same digital data.

Discussion of the Related Art

Prior art in modulation and demodulation teaches various methods ofpulse-width, amplitude, frequency, phase, polarization, andacousto-optic modulation. To achieve higher spectral efficiency, thesemethods are often combined to produce a physical symbol having multiplydefinable and measurable physical characteristics. A symbol withmultiple independently controllable features may be termedmultidimensional, with each physical parameter representing a distinctdimension.

A problem with conventional approaches is the requirement for multiplecircuits operating in parallel to achieve distinct and separatemodulation of each of the several physical attributes. This complicatesboth the transmitter and receiver process and hardware in that thediverse physical attributes being modulated or demodulated requiredistinct and separate means that must be managed simultaneously.

SUMMARY OF THE INVENTION

There is a need for the following embodiments of the invention. Ofcourse, the invention is not limited to these embodiments.

According to an embodiment of the invention, a process comprises:creating a bipolar pulse whose high (up) and low (down) periods areseparately and precisely controllable. According to another embodimentof the invention, a method, comprises creating multidimensional symbolsby conjoining one or more bipolar pulses. According to anotherembodiment of the invention, a method, comprises encoding symbols andtransmitting a signal, wherein a single bipolar pulse with independentlyvariable up and down periods represents a two-dimensional symbol.According to another embodiment of the invention, an apparatus comprisesa symbol encoder. According to another embodiment of the invention, anapparatus, comprises a symbol detector.

These, and other, embodiments of the invention will be betterappreciated and understood when considered in conjunction with thefollowing description and the accompanying drawings. It should beunderstood, however, that the following description, while indicatingvarious embodiments of the invention and numerous specific detailsthereof, is given for the purpose of illustration and does not implylimitation. Many substitutions, modifications, additions and/orrearrangements may be made within the scope of an embodiment of theinvention without departing from the spirit thereof, and embodiments ofthe invention include all such substitutions, modifications, additionsand/or rearrangements.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings accompanying and forming part of this specification areincluded to depict certain embodiments of the invention. A clearerconcept of embodiments of the invention, and of components combinablewith embodiments of the invention, and operation of systems providedwith embodiments of the invention, will be readily apparent by referringto the exemplary, and therefore nonlimiting, embodiments illustrated inthe drawings (wherein identical reference numerals (if they occur inmore than one view) designate the same elements). Embodiments of theinvention may be better understood by reference to one or more of thesedrawings in combination with the following description presented herein.It should be noted that the features illustrated in the drawings are notnecessarily drawn to scale.

FIG. 1 shows a four-dimensional, PWM signal, representing an example ofa type of signal representing an embodiment of the invention.

FIG. 2 is a block diagram of a symbol encoder, representing anembodiment of the invention.

FIG. 3 is a block diagram of a symbol detector, representing anembodiment of the invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiments of the invention and the various features and advantageousdetails thereof are explained more fully with reference to thenonlimiting embodiments that are illustrated in the accompanyingdrawings and detailed in the following description. Descriptions of wellknown starting materials, processing techniques, components andequipment are omitted so as not to unnecessarily obscure the embodimentsof the invention in detail. It should be understood, however, that thedetailed description and the specific examples, while indicatingpreferred embodiments of the invention, are given by way of illustrationonly and not by way of limitation. Various substitutions, modifications,additions and/or rearrangements within the spirit and/or scope of theunderlying inventive concept will become apparent to those skilled inthe art from this disclosure.

The below-referenced U.S. Patent(s) and U.S. Patent Application(s)disclose embodiments that are useful for the purposes for which they areintended. The entire contents of U.S. Pat. No. 7,136,419 [Ref 1] “Pulsewidth communications using precision timing”, United States PatentApplication US 20050123061 [Ref 2] “Multidimensional signal modulationand/or demodulation for data communications”, U.S. Pat. No. 6,445,326[Ref 3] “High speed precision analog to digital converter”, and U.S.Pat. No. 6,850,177 [Ref 4] “Digital to analog converter” are herebyexpressly incorporated by reference herein for all purposes.

This work describes a means of conjoining two or more PWM signalswherein each section of each pulse has a separately determined width (apulse is defined as a signal having a high phase or state followed by alow phase or state). Each logical grouping of n such pulses represents aphysical symbol with 2n dimensions since each of the n high states andeach of the n low states are independently controlled as to their widthsto within some prespecified resolution of the generating circuit. Thereference to a dimensionality of the symbol is supported by the factthat each of the 2n parts comprising the symbol may be independentlyvaried.

In this work, a multidimensional symbol is defined by concatenatingpartial symbols wherein each partial symbol occupies a different timeslot and each part is determined by the same physical property, namelyduration in the preferred embodiment, which varies for each of the 2nparts. The whole symbol occupies the sum of times for each of the 2ntime slots comprising the 2n dimensional signal. Each distinct symbolhas a different duration and it is the set or collection of alldurations that remains constant for a given implementation, each symbolbeing chosen from this set.

In the present invention, there is only one physical property whosechange in state identifies a part of a symbol (not the entire symbol),namely the duration in time of the state or, equivalently, the time ofoccurrence of a transition between a high part and a low part. Thisfeature is responsible for the simplicity of the symbol-generation andidentification circuitry. The identification of a complete symbol isdetermined by convention, namely by a count of transitions between thehigh and low states. This is a subtle but telling distinction betweenthe present invention and those set forth in Ref 1 and Ref 2. The priorart may be thought of as viewing the construction and definition ofphysical symbols by physical properties alone, where a change in any oneof the physical properties listed above determined a symbol boundary.The novelty in the present invention completely removes this restrictionand allows a symbol to be defined logically by counting or setting thenumber of high-low transitions and low-high transitions. The timebetween these transitions acts as the physical carriers of informationin the symbol.

Further, this disclosure teaches a specific means of decoding suchlogical symbols by measuring the physical durations of each part,wherein a part is defined by a rising or falling pulse edge. Theadvantage to communications of data in the presence of noise isdisclosed in Ref. 2, particularly in the discussion of four-dimensionalsymbol constellations. The same concept is used in the presentinvention.

The primary goal of this invention is to provide a method oftransmitting information in the form of a stream of bits over a carrierhaving a bandwidth B at a bit rate that is some multiple of B in asimple and effective manner and detecting or recovering such informationat a receiver. A secondary goal of this invention is to effect suchtransmission and detection as to minimize the error rate in the receivedbit stream. These two goals are to be accomplished under the constraintof simple and low-cost hardware that makes use of standard practices indigital circuit design and manufacture.

In the following, the term “symbol” generally refers to the logicalconstruct either as an abstraction of n numbers arrange as an n-tuple ofintegers as {i, j, k, l}. This term is also used to describe an outputvoltage or signal level of the generating mechanism as well as a logicalportion of the signal being transmitted, received, or decoded. The term“signal” usually refers to a physical voltage level as well as thephysical wave or energy (e.g., RF or light) that is carrying the logicalsymbol as information.

Error Distributions in Timing Measurements

The idea is to compute the error distribution or SNR equivalent formeasurements in the time domain. Sources of error are

-   -   1. Source power fluctuations    -   2. Cross talk between various channels    -   3. Jitter and fluctuations in the symbol generation (time)    -   4. Jitter and offsets in the receiver measurement (time, again).

In the development below, we will assume that these sources of error andnoise, when combined, will produce a jitter in the pulse width (temporaluncertainty in the position of the pulse width or position of its edges)and a jitter in the measuring circuit (temporal uncertainty as to whenthe circuit identifies an edge transition).

The result of the investigations below establish guidelines for both thetransmiter (pulse-generating mechanism) and receiver (pulse-measuringmechanism) and relate the symbol error rate to the jitter in thetransmitter and receiver.

Symbols & Indices

The emitted symbols have the form {i,j,k,l}×delta where i+j+k+l is evenand delta is the time resolution of the generating circuits. There is anoffset of CapDelta for each symbol segment where CapDelta is half thereciprocal bandwidth of the system.

The symbol set with only one increment has eight members (including thesymbol {0,0,0,0}). Here, they are arranged in eight columns with eachsymbol displayed as a vertical column of four numbers. Note the sum ofeach column is an even number.

Suppose the measurement resolution is epsilon, where epsilon ε÷δdelta.Epsilon is chosen to be the smallest resolvable increment in pulse widthat the receiver. Typically, both epsilon and delta are much smaller thanCapDelta. Example: a 10 GHz bandwidth circuit will have a CapDelta of 50ns and a delta of perhaps 10 ns with epsilon of perhaps 5 ns. Take atypical symbol based on these numbers, say {2,3,0,1} and generate asequence of high-low-high-low edge times of 50+10{2,3,0,1} ns or{70,80,50,60} ns which indicates a symbol having 70 ns high, 80 ns low,50 ns high, and 60 ns low portions. This places edges at times 0(rising), 70 ns (falling), 150 ns (rising), 200 ns (falling), and therising edge of the next symbol occurs at time 260 ns. This isillustrated below.

Mapping Bit Patterns onto Symbols

The simplest mapping is to index the symbol set and simply assignsymbols to their respective index values. This would assign binary 0 tosymbol {0,0,0,0), binary 1 to symbol {0,0,1,1} and so forth. This mightbe too simple, however. Suppose we want to reserve {0,0,0,0} for asynchronize pulse or other special case. Also, the number of symbols ina set with index n is not a power of two, except for n=2j−1 for someinteger j>0. This is not a problem, since we will always be needingspecial control symbols that do not represent any binary data.

Guidelines for the Pulse-Generating Circuit (Transmitter)

The idea is to use four timing circuits running in parallel. Thesetimers are loaded with the initial set of numbers. If the symbol is{i,j,k,l} then the first timer is loaded with i, the second with i+j,the third with i+j+k, and the fourth with i+j+j+l. Once loaded, all fourstart simultaneously and the output circuit goes high. As each timertimes out, it generates a clock which changes the state of the outputcircuit. Before the last timer fires, a new set of four numbersgenerated from the next symbol is loaded. Each time has an offset. Ifthe circuit bandwidth is B gigahertz, the offsets are CapDelta for thefirst, 2× CapDelta for the second, 3× CapDelta for the third and 4×CapDelta for the fourth where CapDelta=1/2B ns.

Measuring Pulse Widths in the Presence of Jitter

Each symbol has noise that appears as jitter in the rising and fallingedges. In addition, the receiver circuitry also has noise jitter whichcan assign a symbol edge to the wrong number. Below is an illustrationof a pulse with Gaussian jitter on the rising and falling edges; thejitter has a standard deviation equal to a tenth of the width of thepulse. Note that amplitude noise appears as temporal jitter when thepulse has realistic sloping sides. This will be explored later.

The ideal edge detector would have a decision point at the center of theexpected pulse, shown by the red arrow. Of course, the decision pointalso has jitter, so a better picture would be that of three Gaussiandistributions as shown below.

The actual detection scheme is somewhat different in that a pulse edge,rising or falling, depending on the “polarity” of the circuit, isassigned to an interval represented by an integer. The assignmentintervals are passing by, so to speak, and the edge transition, when itoccurs, selects the most recent interval. One may think of a clockticking, each tick arms the next assignment interval. The edgetransition stops the process, yielding the result of the most recentinterval armed. This is one way of viewing the process. Pictorially, wehave something like the following picture where the pulse is representedby the blue trace, which goes low during interval 2, in this example.

Guidelines for the Measuring Circuit (Receiver)

The measuring circuit should be arranged similarly to the generatingcircuit in that the result of a measurement should not influence theresult of a subsequent measurement. This can only be achieved by usingindependent measuring circuits for each of the four intervals associatedwith a symbol.

A symbol is defined by its four edges. The length of a symbol is thetime between three adjacent rising edges (with two falling edges inbetween). The third rising edge signifies the start of the next symbolas well as the end of the current symbol. The first rising edge seen bythe receiver indicates the arrival of the first symbol and should beused to start four timers conceptually parallel to the generatingcircuit. The first circuit is stopped by the second edge (falling), thesecond circuit is stopped by the third edge (rising), the third circuitis stopped by the fourth edge (falling), and the next rising edge bothstops the fourth timer and restarts the timer chain anew for the nextsymbol. To allow time for read-out, it might be necessary to alternatetwo different timing chains. If we let an edge both stop and start asingle timer or an alternate pair of timers, we run the risk ofincreasing the measurement error by making the starting position of onesymbol segment dependent on the jitter in a previous segment. This willproduce additive errors within a symbol, making the error in the fourthinterval twice that of the first interval. If a timer chain, asdescribed here, is used, the uncertainty will be that of the start of asymbol; this type of error is included in the above calculations.

Symbol Identification [Receiver Discussion]

Introduction

In determining the error from the individual intervals, the geometricalnature of higher dimensions is ignored. In 2 dimensions, the aboveinterval-error determination accounts for the area of the circle aroundthe symbol position but neglects the additional and valid area of thesquare surrounding the circle. Allowing the decision area or volume toextend into this square adds 27%. In 3D, the valid volume nearly doubles(91%), and in 4D the volume of the hypercube is 3.24 times the volume ofthe enclosed hypersphere. It would seem that there is much more signalto be extracted from the noise than the interval assignment methodachieves.

The task is to design a receiver circuit that takes advantage of thisextra decision volume (and does so with efficiency and speed).Conceptually, this is done by measuring the individual intervals andthen computing the distance from the likely centers. In 2D, there are 6candidates, in 3D there are 12, and in 4D there are 24 such nearestneighbors touching any particular center. Note that if the intervalassignment is correct, the equivalent circle or sphere has beenidentified. The corner areas have still been left out. To include thecorner areas, a measurement resolution much smaller than the intervalresolution must be used. Then the closest center wins.

Given a CapSigma-jitter and in interval spacing comparable to thisjitter (instead of 5 to 10 times the jitter as above), the measuringcircuit assigns n numbers to an n-dimensional symbol. Given these nnumbers, which can now each have errors of up to 50% in the assignmentof the particular integers, what type of decision circuit is mosteffective at assigning signals? Are the resulting error ratessubstantially better? For what set of interval-to-jitter parameters? Wewill obviously require a much finer division of intervals than that usedin the transmitter to generate the symbols.

It is only worth doing the analysis if we come up with a fast andeffective receiver circuit. A guess as to the benefits to be gained fromcomparing the volumes (above) is that there is another 5 dB of signal torecover from the noise if the receiver can be made sufficientlysophisticated. This could be well worth the effort for certainapplications.

Divide Intervals into m Subintervals

If each possible generated interval is split into m subintervals, aninterval measurement for a width of n units will yield an integer valueof exactly m×n if there is no noise. Suppose that there is noise

Here, the red distributions represent the sub-interval errors and theblue distribution is at the edge location. The sub intervals are nowclose enough that there is significant overlap from intervals fartherthan the nearest ones. For example, the obvious possibilities are fromA2, A3, A4, and A5 in this case where sub-interval spacing is2×CapSigma. The various distributions are shown at their expectedpositions; in this case, the time of the pulse transition would be mostprobably assigned to sub interval 3, but could be assigned to 2 or 4with appreciable probability and to sub interval 1 or 5 with lesserprobability. These probabilities are computed in the manner used above,but this is not material to the present discussion.

The measurement circuit is designed to produce integers that representthe subinterval selected. These subintervals completely tile each of themain intervals so that if a subinterval within a given main interval isidentified, then the corresponding main interval is necessarily chosen.Thus, for a 2D rectangular lattice, there is no difference between theinterval approach and one based on subintervals. However on 3D and 4Dlattices where the centers are fcc, this is not necessarily the casesince a subinterval measurement could well choose a site with theincorrect parity.

Logic States of the Four-Dimensional Signal

Referring to FIG. 1, showing a four-dimensional signal based onpulse-width modulation of both polarities or amplitude states of anoutput voltage, 101 shows the start time of the signal when the outputgoes high. 102 indicates the time when the first part of the symbol isfinished and the start of the second part with the output going low.Duration 106 indicates the time span of the first part, or dimension 1of the output. 103 indicates the time when the output goes high againspecifying the end of the second part and start of the third part of thesymbol. Duration 107 represents the time span of the second part, ordimension 2. Continuing in this manner, 104 shows the end of third partand the start of the fourth part. Duration 108 represents the time spanof the third part of the signal representing the symbol; this is thethird dimension. 105 represents the end of the fourth part and of thesignal representing the four-dimensional symbol. Duration 109 representsthe time span of the fourth part or dimension. Duration 110 shows theentire duration of the signal encoding the four-dimensional symbol.

Continuing with the example of a four-dimensional symbol, the preferredembodiment of the invention, the start of the next symbol occurs at theend of the preceding symbol, namely the point 105 in FIG. 1.

It will be recognized that adding (removing) one such part increases(decreases) the dimensionality of the symbol by one. For example, FIG. 1can equally well represent two conjoined two-dimensional signals, asingle four-dimensional signal, or half of an 8-dimensional symbol,among other obvious combinations. It is possible to createodd-dimensional symbols, but they would have an undesirable property ofalternate transitions directions at starting and stopping points.

Information Encoding in a Four-Dimensional Symbol

The timing circuitry to be discussed below necessarily has finiteresolution. That is, the physics of the devices used limit the precisionof temporal division to a certain time interval below which it isimpossible to distinguish different, closely space time intervals. Thislimit is due to the bandwidth that the wires, cable, or circuit tracesimpose as well as by the inherent jitter in the component devicescomprising the various circuits.

Suppose that this limit is represented by the letter [[greek lettermu]]μ (for “measures” expressed in some time units). Then a pulse(either high or low) with length k μ, where k is an integer greater than1, can be reliably distinguished from one that is (k+1) μ or (k−1) μ induration, but not from a pulse whose width lies between k μ and (k±1) μ.

Let the resolution of the signal-generation circuit be 5; that is 0≦k≦4so that there are five distinguishable width states to each part of asymbol. Suppose further that we choose a symbol constellation based on aface-centered cubic (fcc) grid. A symbol has the tuple representation asabove of {i, j, k, l} with each integer index ranging from 0 to 4. Thefcc constraint demands (for purposes of higher noise immunity) that thesum i+j+k+l is an even number. Under these conditions, there will be 313distinct symbols in the constellation. Reserve 256 of these symbols fora mapping between the 256 8-bit binary integers, leaving 57 possiblesymbols either unused or reserved for control symbols such as an idlesymbol representing no information being transmitted, among otherpossibilities.

As shown in Ref 2, there are approximately twice as many symbols in arectangular lattice, where each lattice point has an assigned symbol,than in the ffc case where the odd lattice points are intentionally leftunassigned. Thus, the bit rate for the rectangular case is one more thatfor the fcc case, but the fcc case has higher noise immunity at the costof this one bit.

Symbol Generating Method for a Four-Dimensional Signal

Referring to FIG. 2 showing a block diagram of a mechanism forgenerating a four-dimensional signal, 201 indicates the input bitstream, which may be either serial or parallel. This bit stream mayoriginate in any number of physical devices such as computer memory orfirst-in-first-out (FIFO) buffer and is represented physically by asequence of logic levels (high-low voltages) standing for digital dataand encoded as the usual ones and zeros. Bit stream 201 enters symbolconstructor 202 where it is parsed and encoded into four parts, eachpart representing a dimension of the logical symbol being assembled.

Symbol constructor 202 is a hardware realization of a mapping between apredetermined grouping of bits in the input stream to four integersrepresenting the symbol. In the example above, each 8-bit group parsedfrom the input stream is mapped to a symbol specified by a 4-tuple ofintegers each between 0 and 4. Symbol constructor 202 produces a singlefour-part symbol from each grouping of 8 bits and partitions these fournumbers into two groups. The first group, consisting of the integers iand i+j is presented via connections 203 and 204 to parallel timingcircuits 205 and 206, respectively. The second group, consisting of theintegers i+j+k and i+j+k+l, is held for conversion of the second half ofthe symbol. Symbol constructor 202 contains the necessary output buffersto keep the output of the symbol generator of FIG. 2 busy at all times.If there are no data on input 201, the symbol constructor prepares astream of idle symbols for conversion by the timing circuits.

Symbol constructor 202 presents coded symbol integers on an as-neededbases to symbol timers 205 and 206. When a coded symbol part is removedfrom the input buffer of timer 205 or timer 206, timer control 213requests symbol constructor 202 for another symbol part via control line212. In this way, the presentation of coded symbol parts and conversionto pulse width is synchronized on an as-need basis so that the symbolstream at output 211 is not interrupted.

When the symbol. has been encoded by 202 and the first half transmittedto the timing stages 205 and 206, the conversion in these timing stagesis initiated whereupon a start signal on control line 209 sets theoutput of gate circuit 210 to high. This action is simultaneous with theoutputs 207 and 208 of timer stages 205 and 206 going high. That is,upon a “ready” signal generated in timer control 213, the output 211 ofthe symbol generator of FIG. 2 goes high as do lines 207 and 208, whichare inputs to gate circuit 210.

Output 207 of the first timing circuit 205 stays high for a period of[[greek letter tau sub 1]] τ₁=Δ+μ i units of time, where Δ is abandwidth-dependent constant. At the end of this period, output 207switches state to low. Similarly for the second timing circuit 206;output 208 stays high for a period of τ₂=2 Δ+μ(i+j) units of time. Atthe end of this second period, output 208 switches state to low.

Gate circuit 210, which previously switched its output state on outputline 211 from low to high upon the “start” control supplied by line 209(simultaneously with lines 207 and 208 going high), effects a change instate on the output line 211 each time one of its input lines, 207 or208 changes state. When output 208 changes state, the timer control 213starts pulse width conversion for the next half of the symbol. Thissecond half, noted above by i+j+k and i+j+k+l, is ready for conversionas it had already presented by symbol constructor 202 on lines 203 and204 to timer stages 205 and 206. However, during this second half of thesignal, the first timing circuit 205 now stays high for a period τ₃=3Δ+μ(i+j+k) units of time and timing circuit 206 stays high for a periodτ₄=4 Δ+μ(i+j+k+l) units of time. This second half of the symbol iscontrolled as described for the first half, the only difference beingthe a 3Δ and 4Δ added to the integers presented by symbol constructor202.

As the final part of the completed symbol is determined by line 208going low for the second time, a new symbol is ready for conversion andthe process repeats.

In this manner, gate circuit 210 presents a continuous stream of encodedpulses as a symbol stream on output 211 This symbol stream is acontinuous sequence of two-state pulses, where each state has adiscretely variable width. This stream may be appropriately amplifiedand used to modulate a laser (light source) or any other useful carrierof information.

By following the logic of the above-described circuits, it is may berecognized that a wave form of the kind represented in FIG. 1 may begenerated. It is also evident that this waveform may be indefinitelyrepeated according to data presented to the circuit on bit stream 201,effecting a continuous conversion of binary digital data to an encodedform pulses representing a sequence of multidimensional symbols. Analternate embodiment is to use four timing circuits instead of two. Inthis version, symbol constructor 202 sends all four parts to four timerstages instead of two. Simply view timers 205 and 206 as dualindependent timers each with two inputs and two outputs. The preferredembodiment of two timers is a simpler circuit and is just as effectiveat symbol conversion as the four-stage version. There is no innovativestep in changing from four timers to two timers as equivalence betweenthe two versions is readily apparent to anyone familiar with commonpractices of circuit design.

Parameter line 214 allows the number of dimensions to be set,essentially determining how many n Δ times are added to each timer state205 and 206 before resetting at the start of a new symbol. Otherinformation provided on parameter line 214 concerns the delay step sizesΔ and μ as well as controlling the operation of the symbol generator,allowing it to be stopped completely or restarted as needed.

From this discussion, it is evident that symbols of any (even)dimensions of 2 or above can be constructed and assembled in thismanner.

Parameter line 215 loads symbol constructor 202 with informationconcerning the number of states and the dimensions of the symbols to bemapped. Alternatively, a complete symbol table map can be downloadedinto symbol constructor 202 via line 215. That is, the symbol table maybe either mapped or computed by the constructor 202, depending on theparticular design.

Each of the timer circuits 205 and 206 are based on the invention of Ref4 where a method of controlling pulse widths based on digitalinformation is disclosed.

Detecting Signals and Decoding Symbols

The symbol stream generated by the circuit of FIG. 2 may be used tomodulate an appropriate carrier. In this way, information may betransmitted to another location or device. At the receiving device,assume that means to demodulate the carrier are employed. Thedemodulated signal, in the form of a stream of pulses, is passed to adecoding circuit that measures the durations between each voltage-statetransition thereby decoding the pulses into a stream of symbols andthence to a stream of bits representing the original data.

For example, the bit stream might be a digital message sent over a lightbeam from one part of a communication system to another. The light ispulse-encoded as a sequence of high-intensity light follow bylow-intensity light states, each state has a prescribed duration. At thereceiving end, one typically employs a photodiode that puts out ahigh-voltage state in response to the high-intensity part, followed by alow-voltage state in response to the low-intensity part. The bandwidthof both the transmitting side and the receiving side determine theminimum pulse width A as noted above.

The symbol-detection circuit is based on the invention of Ref 3, whichdiscloses a high-speed converter for converting a pulse width to abinary integer. The detection circuit required to provide the requiredconversion must have at least a resolution of the value μ used togenerate the transmitted signals. Let δ be the resolution of thedetection circuit. Preferably δ will be some fraction of μ such as onehalf or one third. This will enable the detection circuit to assign avalue within an error of ±μ instead of ±μ, allowing a conversion processwith higher accuracy.

Referring to FIG. 3, pulse stream, 301 consisting of a sequence ofrising and falling edges of a voltage level, is applied to the edgedetector 302, which generates a precise timing signal (a narrow pulse)each time the input stream changes state (high-to-low, or low-to-high).This timing pulse is applied to each of two counters 304 and 305 viainput line 303. Upon initialization, via line 312, counter 304 is gatedoff via line 313 and counter 305 is gated on via line 314 (logic gates,not shown, are included in each of the circuits responding to theinitialization signal). Thus, counter 304 is stopped and counter 305 isrunning. The first pulse generated by the edge detector 302 causes thecounters to reverse state. That, counter 304 is started and counter 305is stopped. The next pulse generated by edge detector 302 reverses thestate of the counters once more, so that counter 304 is stopped andcounter 305 is started. This state-reversal process continues as eachtiming pulse is generated by edge detector 302.

When counter 304 is stopped, its count in the form of a coded integer,typically small between 2 and 8 bits, is presented to interleave circuit308 via line 306, and the counter 304 is reset to await its next startsignal. Similarly, when counter 305 is stopped, its count in the form ofa coded integer, typically small between 2 and 8 bits, is presented tointerleave circuit 308 via line 307, and the counter 305 is reset toawait its next start signal. In this way, an alternating sequence ofcoded integers is presented to interleaver 308 which assembles them inthe correct order in its symbol buffer (not shown). Initializationsignal via line 315 has previously cleared the symbol buffer ininterleaver 308 and ensured that the first integer from counter 305 vialine 307 is ignored. Thus, the first integer stored into the symbolbuffer in interleaver 308 represents the time interval of the firstpulse in the pulse stream measured following the initialization signalon line 312.

To ensure that the symbol decoder of FIG. 3 has started on the correctphase or state of the symbol presented, common practice known todesigners in the field of pulse-controlled timing circuitry is totransmit a null signal at the beginning of each communication. Thesystem then synchronizes its activities based on known and pre-specifiedproperties of a null sequence. Since this is well understood in the art,details of such spchronization circuitry are not discussed and will beassumed to follow common practice.

At the completion of each symbol residing in the symbol buffer ininterleaver 308, the buffer contents are passed to the mappingcircuitry, map 310. Map circuit 310 has been previously set to aninitial state via the initialization signal on line 316. Prior toinitialization, a map particular to the symbol type being decoded hasbeen loaded into map circuit 310 via line 317. Thus, the map circuit 310is ready to receive groups of symbol integers as described above. Forthe four-dimensional case of the preferred embodiment, the receivedsymbol is in the form of a 4-tuple of small integers. The function ofthe map circuit 310 is to use those four numbers as indices into alook-up table, namely the map that had been previously loaded via line317. The function of the map look-up is to convert or map the 4-tuple ofsmall integers into a single integer representing the index or name ofthe converted symbol. In the preferred embodiment of a symbolconstellation having 256 or more symbols, this is a binary integer inthe range of 0 to 255. This binary number is sent to the output where itbecomes part of the integer stream on line 311.

An alternate method to remap the 4-tuple representing the symbol is toperform some simple arithmetic on the four integers. A simplecalculation then converts the 4-tuple of integers into a binary integerby a series of shifts (doublings) and concatenation of the four pieces.

An alternate embodiment of the circuit in FIG. 3 is to use four countercircuits instead of two. In the four-counter version, each counter sendsits integer to the map circuit 310 and the symbol is then complete afterthe fourth counter has transferred its information. The preferredembodiment of two counters is a simpler circuit and is just as effectiveat symbol decoding as the four-counter version. There is no innovativestep in changing from four counters to two counters as equivalencebetween the two versions is readily apparent to anyone familiar withcommon practices of circuit design.

CONCLUSION

The described embodiments and examples are illustrative only and notintended to be limiting. Although embodiments of the invention can beimplemented separately, embodiments of the invention may be integratedinto the system(s) with which they are associated. All the embodimentsof the invention disclosed herein can be made and used without undueexperimentation in light of the disclosure. Although the best mode ofthe invention contemplated by the inventor(s) is disclosed, embodimentsof the invention are not limited thereto. Embodiments of the inventionare not limited by theoretical statements (if any) recited herein. Theindividual steps of embodiments of the invention need not be performedin the disclosed manner, or combined in the disclosed sequences, but maybe performed in any and all manner and/or combined in any and allsequences. The individual components of embodiments of the inventionneed not be formed in the disclosed shapes, or combined in the disclosedconfigurations, but could be provided in any and all shapes, and/orcombined in any and all configurations. The individual components neednot be fabricated from the disclosed materials, but could be fabricatedfrom any and all suitable materials. Homologous replacements may besubstituted for the substances described herein. Agents which are bothchemically and physiologically related may be substituted for the agentsdescribed herein where the same or similar results would be achieved.

Various substitutions, modifications, additions and/or rearrangements ofthe features of embodiments of the invention may be made withoutdeviating from the spirit and/or scope of the underlying inventiveconcept. All the disclosed elements and features of each disclosedembodiment can be combined with, or substituted for, the disclosedelements and features of every other disclosed embodiment except wheresuch elements or features are mutually exclusive. The spirit and/orscope of the underlying inventive concept as defined by the appendedclaims and their equivalents cover all such substitutions,modifications, additions and/or rearrangements.

The appended claims are not to be interpreted as includingmeans-plus-function limitations, unless such a limitation is explicitlyrecited in a given claim using the phrase(s) “means for” and/or “stepfor.” Subgeneric embodiments of the invention are delineated by theappended independent claims and their equivalents. Specific embodimentsof the invention are differentiated by the appended dependent claims andtheir equivalents.

What is claimed is:
 1. An apparatus, comprising an electrical circuitdecoder coupled to a receiver wherein the decoder unit, upon receiving astandard well known null starting signal at the beginning of eachcommunication, receives a variable pulse width bit stream sequence ofthe rising and falling edges of precisely timed rising and fallingvoltage level time domain symbol encoded electrical, light or otherphotonic pulses from the receiver and directs the signal or signals toan edge detector that generates a precise timing pulse each time theinput changes state from high-to-low or low-to-high and applies thesealternating timing pulses to its two or more counters via an input lineto each counter thereby initializing the counters and gating them to thealternate processing of the counting of the durations of theirrespective encoded time domain signals to be transferred in the form ofcoded signals constructed by the counters from their signal input to theinterleaving section of the apparatus that then assembles thedeconcatenated symbols back into their original form as sum concatenatedtime domain symbols wherein the measurement of the time that had beencaptured during the duration between the initiation of the high time andits subsequent end and the separate duration of the initiation of thelow time and its subsequent end of the variable pulse widths of thesymbols have been recreated without any symbolic meaning being attachedto the rise and fall times of the variable bipolar pulses except throughtheir use in the initiation and termination of the signal or the set ofsignals that are then sent to the mapping circuitry of the apparatus toits constellation of binary tables and converted to an exit symbol forthe integer stream exit.